I noticed that not only is the additional output hardware latency missing, but insert sends, e.g. in the master bus, are not taken into account either.
It looks like you've implemented what's possible.
The complete solution will be a configuration option, which isn't too urgent, but I'm looking forward to it.
I noticed that not only is the additional output hardware latency missing, but insert sends, e.g. in the master bus, are not taken into account either.
It looks like you've implemented what's possible.
The complete solution will be a configuration option, which isn't too urgent, but I'm looking forward to it.